Digital Systems and Signal Processing

Learning Outcomes

Subject Specific Intellectual and Research Skills

Having successfully completed this module you will be able to:

• Build and debug a digital circuit
• Design testbenches to verify your design
• Understand the the characteristics of stochastic signals and the ideas of sampling, quantisation and coding within the context of communications signals
• Describe state machines of moderate complexity in SystemVerilog, simulate and synthesise into hardware
• Develop CPLD and FPGA implementations of combinational and sequential digital systems
• Create a digital representation of an analogue signal, which is suitable for use in communication systems
• Develop working knowledge of state-of-the-art commercial software tools for digital system design
• Compress the digital representation of an analogue signal and protect it from transmission errors

Transferable and Generic Skills

Having successfully completed this module you will be able to:

• Address novel design challenges by choosing appropriate analysis and design methods
• Present results of design work in a formal report

Knowledge and Understanding

Having successfully completed this module, you will be able to demonstrate knowledge and understanding of:

• Sequential digital system design for implementation in CPLDs and FPGAs
• Stochastic signals and their signal processing in communication systems, including sampling, quantisation and coding
• The principles of Design for Test and apply them in practice

Communications part (14 lectures):

Characterisation of Stochastic Signals

• Probability and cumulative density functions (PDF / CDF), auto- and cross-correlation, power spectral density, stochastic quantities and filtering

Sampling and Quantisation:

• Analogue-to-digital conversion
• Sampling: Nyquist criterion, frequency domain
• Aliasing
• Baseband and bandpass sampling
• Quantisation and signal-to-noise ratio
• Digital-to-analogue conversion
• Reconstruction filtering

Source and channel coding

Digits (22 lectures):

• Analysis and Design of Synchronous State Machines
• RTL synthesis of standard Combinational and Sequential Building Blocks
• Introduction to SystemVerilog assertion-based verification
• Software tools for CPLD and FPGA synthesis
• Implementation of Basic Microprocessor-Core Blocks:

Registers, ALU, SRAM, IO ports, Instruction Decoder

Synthesis of a simplified MIPS microprocessor on FPGA

• Design for Testability:

Testing combinational and sequential digital systems

Boundary Scan

Build-in self-test

Summative

This is how we’ll formally assess what you have learned in this module.

Referral

This is how we’ll assess you if you don’t meet the criteria to pass this module.

Repeat

An internal repeat is where you take all of your modules again, including any you passed. An external repeat is where you only re-take the modules you failed.