Module overview
Describe the design of complex digital systems using a (SystemVerilog and SystemC based) behavioural synthesis approach.
Provide understanding of the algorithms which underpin behavioural synthesis including scheduling, allocation and binding.
Gain hands-on experience in the application of behavioural synthesis to generate designs optimised for user-defined constraints.
Describe digital design for testability techniques at the behavioural and RTL levels.
Provide an overview of emerging SoC design and test methods.
Describe system level low power design methods.
The module will use the hardware description language SystemVerilog (and also SystemC), introduced in ELEC6236 Digital System Design.
Linked modules
Pre-requisites: ELEC3221 OR ELEC6259
Aims and Objectives
Learning Outcomes
Knowledge and Understanding
Having successfully completed this module, you will be able to demonstrate knowledge and understanding of:
- Advanced digital synthesis techniques including low power techniques, the use of SystemVerilog and SystemC in digital system design
Disciplinary Specific Learning Outcomes
Having successfully completed this module you will be able to:
- Gain understanding of modern emerging System-on-Chip design methods
Subject Specific Practical Skills
Having successfully completed this module you will be able to:
- Hands-on experience of optimised behavioural synthesis for user defined constraints, such as power consumption, performance, size
Subject Specific Intellectual and Research Skills
Having successfully completed this module you will be able to:
- Understand techniques for digital system behavioural synthesis, verification and performance evaluation
Syllabus
Review of hardware description languages and behavioural synthesis of digital systems (SystemVerilog, SystemC, Bluespec).
Behavioural synthesis data structures and algorithms
- Data and control flow representations
- Data flow graph (DFG) descriptions
- Control data flow graph (CDFG) descriptions
- Extended Petri-net models
Synthesis and design space
- Design space exploration
- Constructive vs. transformational/iterative techniques
- Behavioural optimisation
- Scheduling, allocation, module binding and controller synthesis
Scheduling and binding algorithms
- Unconstrained and constrained scheduling
- Scheduling of multicycled and pipelined functional modules
- Allocation and binding algorithms
- Interconnect allocation and optimisation
- Overview of transformational/iterative approaches (simulated annealing, genetic algorithms)
Design for testability
- Design for Testability: scan-based and built-in-self-test (BIST) techniques
- Test scheduling, test controllers, on-line test
Low power design of IP core for SoC applications, development of a high-level synthesis system.
Learning and Teaching
| Type | Hours |
|---|---|
| Completion of assessment task | 22 |
| Wider reading or practice | 34 |
| Revision | 10 |
| Follow-up work | 18 |
| Preparation for scheduled sessions | 18 |
| Tutorial | 12 |
| Lecture | 36 |
| Total study time | 150 |
Resources & Reading list
General Resources
SystemC Quick Reference Guide.
Textbooks
Sabih Gerez. Algorithms for VLSI design automation. Wiley.
Black, D.C., Donovan, J., SystemC (2004). from the Ground Up. Kluwer Academics.
Gajski, D.D., Abdi, S., Gerstlauer, A., Schirner, G (2009). Embedded System Design. Springer.
John P Elliott. Understanding behvioural synthesis. Kluwer.
Zwolinski M (2009). Digital System Design with SystemVerilog. Pearson Prentice Hall.
Andrew Rushton. VHDL for logic synthesis. Wiley.
Giovanni De Micheli. Synthesis and optimisation of digital circuits. McGraw Hill.
Mark Zwolinski. Digital system design with VHDL. Prentice-Hall.
Assessment
Assessment strategy
Laboratory sessions are scheduled in the labs on level 2 of the Zepler building
Length of each session: 15 minutes
Number of sessions completed by each student: 1
Max number of students per session: 8
Demonstrator:student ratio: 1:1
Preferred teaching weeks: 10 to 11
Summative
This is how we’ll formally assess what you have learned in this module.
| Method | Percentage contribution |
|---|---|
| Continuous Assessment | 50% |
| Final Assessment | 50% |
Referral
This is how we’ll assess you if you don’t meet the criteria to pass this module.
| Method | Percentage contribution |
|---|---|
| Set Task | 100% |
Repeat
An internal repeat is where you take all of your modules again, including any you passed. An external repeat is where you only re-take the modules you failed.
| Method | Percentage contribution |
|---|---|
| Set Task | 100% |
Repeat Information
Repeat type: Internal & External