Module overview
The following topics will be covered:
- How SystemVerilog is interpreted for simulation and synthesis
- How to use EDA tools to configure FPGAs
- The principles of functional verification of digital systems
- The principles of Built-In Self-Test and system-level design for test techniques.
- The module will introduce you to the industry-standard hardware description language System Verilog (and to SystemC).
Aims and Objectives
Learning Outcomes
Knowledge and Understanding
Having successfully completed this module, you will be able to demonstrate knowledge and understanding of:
- How to include design for test structures in a sequential digital system
- Describe sequential digital systems in a hardware description language.
Subject Specific Practical Skills
Having successfully completed this module you will be able to:
- Validate a digital system using a simulator
- Synthesise a digital system to an FPGA
Subject Specific Intellectual and Research Skills
Having successfully completed this module you will be able to:
- Generate tests for a combinational digital circuit
- Know how to model circuits and systems in SystemVerilog.
Syllabus
- Hardward Description Languages: SystemVerilog
- Basic building blocks and language constructs
- Register Transfer-Level Design
- Controller/datapath partitioning
- Synthesising designs to FPGAs
- Simulation and synthesis principles
- Test generation and design for test
- Built in Test: Principles, structures, signature analysis
- Multiple Clock Domains: Transferring data between clock domains.
Learning and Teaching
Type | Hours |
---|---|
Supervised time in studio/workshop | 6 |
Follow-up work | 15 |
Lecture | 30 |
Wider reading or practice | 55 |
Revision | 10 |
Completion of assessment task | 19 |
Preparation for scheduled sessions | 15 |
Total study time | 150 |
Assessment
Assessment strategy
Laboratory sessions are scheduled in the labs on level 2 of the Zepler building
Length of each session: 3 hours
Number of sessions completed by each student: 1
Max number of students per session: unlimited
Demonstrator:student ratio: 1:12
Preferred teaching weeks: 6 to 7
Summative
This is how we’ll formally assess what you have learned in this module.
Method | Percentage contribution |
---|---|
Design Exercise | 20% |
Examination | 70% |
Laboratory | 10% |
Referral
This is how we’ll assess you if you don’t meet the criteria to pass this module.
Method | Percentage contribution |
---|---|
Examination | 100% |
Repeat
An internal repeat is where you take all of your modules again, including any you passed. An external repeat is where you only re-take the modules you failed.
Method | Percentage contribution |
---|---|
Examination | 100% |
Repeat Information
Repeat type: Internal & External